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[Not Applicable]
One embodiment of the present invention relates to memory cell and memory architecture design. More specifically, one embodiment of the present invention relates to distributed, configurable modular predecoders used in memory architecture.
Memory architectures typically balance power and device area against speed. High-performance memory architectures thus may place a severe strain on the power and area budgets of associated systems, particularly where such components are embedded within a VLSI system, such as a digital signal processing system for example. Therefore, it is highly desirable to provide a memory architecture that is fast, yet power and area-efficient.
Predecoder blocks are used to perform the first layer of address predecoding, generating the signals used by local decoders (alternatively referred to as xe2x80x9clocal x and y decodersxe2x80x9d or xe2x80x9cx and y decodersxe2x80x9d) to select specific rows and columns in a memory cell array, and thus select specific memory cells. The parameters of the predecoder block are dependent on how the memory is partitioned. For example, the parameters of the predecoder block are dependent on the number of rows in a subblock, number of subblocks, multiplexing depth, etc. If the predecoder block is implemented in a single contiguous area, the amount of area will vary depending on the exact memory partitioning employed.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
One embodiment of the present invention relates to a hierarchical memory structure having distributed, highly configurable modular predecoding. In this embodiment, the hierarchical memory structure includes a first predecoder adapted to perform a first layer of address predecoding and at least one second predecoder interacting with the global predecoder and adapted to perform a second layer of address predecoding.
Another embodiment of the present invention relates to a hierarchical memory structure, a first predecoder, at least two second predecoders and at least one decoder. In this embodiment, the first predecoder includes block select information and the two second predecoders interact with at least the first predecoder. Further, the decoder is adapted to interact with at least the second predecoders. In this embodiment, the first predecoder is adapted to perform a first layer of address predecoding while the second predecoders are adapted to perform a second layer of predecoding.
Yet another embodiment relates to a memory device comprising a synchronous controlled global element and a self-timed element. In this embodiment, the synchronous controlled global element comprises a global predecoder while the self-timed local element comprises at least one local predecoder interfacing with the synchronous controlled global element. In another embodiment, the global element may further comprise at least one global decoder, a global controller and/or global sense amplifier. In another embodiment, the local element may further comprise a plurality of memory cells forming at least one cell array.
Another embodiment of the present invention relates to a hierarchical memory structure having at least two areas. The first area is adapted to receive global predecoder circuits that may vary slightly from memory to memory. The second area is adapted to receive local predecoder circuits.
In yet another embodiment of the present invention, pluralities of additional areas are contemplated. These additional areas, like the second area, are adapted to receive local predecoder circuits.
One embodiment of the present invention relates to a method of optimizing predecoder circuitry distribution in a structure. This embodiment comprises locating predecoder circuitry that varies little from structure to structure in the structure separate from other (i.e., local) predecoder circuitry.
Other aspects, advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawing, wherein like numerals refer to like parts.